Circuits and devices for regulating a voltage level of a control signal in MOS transistors or the like are known. Voltage limiting devices and circuits may be used for protecting an EPROM or EEPROM or arrays of such devices, as in a PLD. During programming of an EPROM or EEPROM, a voltage limiting device controls the program voltage to prevent damage or misprogramming that could occur if the program voltage were to be allowed to increase beyond a predetermined value. Other applications for voltage limiting devices include use with structures, such as a transmission gate transistors, for which performance may be improved by providing a boosted voltage. A voltage limiting device may be used to control the gate of the transmission gate transistor so as to prevent the boosted voltage from reaching a level which would overstress the gate oxide of the transistor.
A top view of a grounded-gate voltage limiting device is shown in FIG. 1. A gate polysilicon layer 10 extends above a drain electrode 12 that is formed by diffusing n-type dopant into a semiconductor substrate 14. The semiconductor substrate is a p-substrate, which is held at ground potential. The areas surrounding the drain electrode 12 have an additional p-type implant to prevent lateral leakage to adjacent transistors. That is, the p-type implant is a field stop implant. The device may include a source 16, but no connections are made to the source, thereby allowing the source to "float."
While not shown, the polysilicon gate layer 10 is spaced apart from the drain electrode 12 by a gate oxide layer. An opening is formed in a dielectric layer, not shown, that is atop the drain electrode. The opening permits direct contact of a metallic interconnect 18 with the drain electrode.
The voltage limiting device of FIG. 1 is shown schematically in FIG. 2. The metallic interconnect 18 is shown as an input node. The input node may be connected to a source of a boosted voltage to regulate the voltage. For example, a program mode voltage for an EPROM may be regulated using the device. When the program mode voltage is sufficiently low, a breakdown will not occur and no current will flow from the drain electrode 12 to the grounded gate 10. Upon reaching the breakdown voltage, current begins to flow from the drain electrode to the substrate 14. The initiation of current flow limits the voltage at the input node.
Ideally, the device clamps the program mode voltage at the breakdown voltage of the device, so that any increase in power results in increased current while the voltage remains fixed. Steep current-voltage (I-V) curves are obtainable, but practical limitations prevent designers from achieving the ideal. Referring to FIG. 3, the breakdown voltage of the device of FIG. 1 is reached at approximately 13.8 volts. Below this voltage level, no current flows from the metallic interconnect 18 to the grounded substrate 14. Beyond the breakdown voltage, there is control of voltage increases, but the control is significantly improved only upon reaching approximately 15.3 volts. That is, the current-voltage (I-V) characteristics of the device are significantly improved after the voltage at the metallic interconnect 18 reaches 15.3 volts.
In many applications, the lower portion 20 of the I-V curve may have no adverse effect on the desired protection of other circuitry. Where the circuitry to be protected is able to withstand voltages up to 18 volts or more, the device of FIG. 1 may be reliably employed. On the other hand, circuitry that is damaged or rendered less reliable by voltage levels exceeding 14 volts are not provided adequate protection by the device of FIG. 1.
It is an object of the present invention to provide a grounded-gate voltage limiting device having improved I-V characteristics.